1. Field of the Invention
This invention relates to improvements in phase-locked loop circuitry and methods for operating same, and to improvements in circuitry and methods for reducing steady state error and increasing the capture range of a PLL during convergence by automatically changing the gain applied to the signal from the phase detector.
2. Technical Background
This invention pertains to phase-locked loop circuits of the type that use a phase detector, an integrating filter, and a variable frequency circuit in a feedback configuration to track accurately an input signal at a reference frequency. In a broad sense, the variable frequency circuit can be a voltage-controlled oscillator (VCO), but in the embodiment illustrated herein, the variable frequency circuit includes a variable speed motor and a generator that produces a signal of frequency dependent upon the speed of the motor. The phase of the variable frequency signal with respect to the reference frequency is determined by the phase detector, and the phase detector generates a dc voltage signal, which may be filtered by the integrating filter, to control the variable frequency signal, for example, by controlling the frequency of a VCO or by controlling the speed of the motor. The voltage signal forces the VCO to compensate, or changes the speed of the motor, when the variable frequency drifts from the reference frequency.
Typically when the PLL begins operation, the variable frequency requires a certain time to converge to the frequency of the input signal, until "lock" occurs. When lock occurs, the variable frequency tracks the input signal, and the PLL circuit functions in a feedback mode to maintain the lock. As known in the art, a higher gain applied to the signal from the phase detector reduces the steady state operation error. On the other hand, a low gain applied to the phase detector output signal widens the lock, or capture, range.
What is needed is a circuit and method that will provide a lower gain when the phase error between the reference frequency and the variable frequency is large, during convergence, and a higher gain when the phase error is low, when lock has been, or is close to being, attained. The circuit and method should provide multiple break points (changes in the gain) in the transfer function if desired, so that a smooth and approximately linear change of phase detector output voltage is obtainable, and the PLL performance can be maximized.